CAPACITANCES IN THE BACKEND OF A 100nm CMOS PROCESS AND THEIR PREDICTIVE SIMULATION

One of the challenging issues for semiconductor circuit design is how to overcome RC delays in the interconnect layers. To reduce the overall dielectric constant, it is important to develop a low-k barrier/etch stop film that can prevent the metal lines, usually made of aluminum, from interacting with other materials in multilevel interconnect schemes. An additional requirement for a barrier/etch stop film is high etch selectivity with respect to the ILD (interlayer dielectric). Silicon nitride has been generally accepted as a first generation barrier. However, its k-value is high and when used in conjunction with a lower k dielectric, the overall k-value of the stack is significantly impacted. Here voids may serve a beneficial purpose, where they can lower the overall capacitance. In this paper the simulation of backend and interconnect capacitance is considered. The backend stack is built up using topography simulation of deposition, etching, and CMP (chemical mechanical planarization) processes in different metal lines. We present results for a 100nm CMOS process. We show that the influence of void formation between interconnect lines strongly impacts the whole interconnect stack performance. Our tool for the topography simulations is called ELSA (enhanced level set applications) whose outputs are used by the capacitance extraction tool called RAPHAEL. The results of RAPHAEL are made available to the circuit designer in turn and are used in SPICE. TAGUNGSBAND MIKROELEKTRONIK 2003 Seite 482